1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of metal lines formed in a low-k dielectric material, wherein the dimensions of the metal line trenches may be defined by a 193-nm lithography technique.
2. Description of the Related Art
The fabrication of an integrated circuit is a highly complex process requiring up to 500 or even more single process steps for sophisticated semiconductor devices, such as microprocessors, storage devices, ASICs (application specific integrated circuits) and the like, wherein one of the most critical process steps is the lithographical imaging of a specified circuit pattern provided on a mask or reticle into a resist layer formed on a substrate and the subsequent patterning of the resist layer. The patterned resist layer is then used as a mask for the subsequent patterning of underlying material layers by, for instance, anisotropic etch procedures, ion implantation and the like.
In the field of manufacturing integrated circuits, there is an ongoing drive to steadily decrease the feature sizes of circuit elements so that reproducible and robust processes have to be continuously established and/or adapted to more sophisticated process constraints. Presently, advanced integrated circuits that are available as mass products include circuit elements having dimensions which are well below the optical resolution of the lithography apparatus used for imaging a pattern from the reticle to the specified material layer formed on the substrate. The formation of circuit elements with dimensions less than the wavelength of the exposure radiation used for the lithography is based on a highly non-linear behavior of the resist materials used and on other process techniques, such as trim etch processes and the like. In spite of non-optical process techniques for reducing dimensions of resist features or obtaining minimum feature sizes, it is, however, nevertheless necessary to also reduce the exposure wavelength corresponding to the desired minimum critical dimensions to maintain the required accuracy in these subsequent processes. Minimum dimensions of circuit elements in sophisticated semiconductor devices are presently less than 100 nm, wherein the exposure wavelength is currently being transferred from 248 nm to 193 nm, thereby rendering a plurality of processes that are well established at an exposure wavelength of 248 nm as non-compatible with design and process requirements, for instance in view of reliability and production yield.
As noted above, the total resolution of reliably transferring circuit patterns from a lithography mask to a substrate is determined, on the one hand, by the intrinsic optical resolution of the photolithography apparatus, the characteristics of materials involved in the photolithography patterning process, such as the photoresist and any anti-reflective coatings (ARC) that are provided to minimize deleterious scattering and standing wave effects in the photoresist, and by deposition and etch procedures involved in forming the resist and ARC layers and etching these layers after exposure. In particular, the highly non-linear behavior of the photoresist in combination with sophisticated ARC layers and lithography mask techniques allows the formation of resist patterns having dimensions considerably below the intrinsic optical resolution of the photolithography apparatus. Since the plurality of process steps involved in finally obtaining a circuit element of specified dimensions mutually influence each other, the change of one process or material may typically require great effort in establishing a new appropriate process sequence that conforms with the new design and process requirements.
The development of integrated circuits of increased functionality and enhanced performance not only necessitates the reduction of critical feature sizes but also the introduction of new materials. One important aspect in enhancing the performance of integrated circuits is the reduction of parasitic capacitances to reduce a signal propagation delay caused by the intrinsic line resistance and the parasitic capacitance between neighboring metal lines. Consequently, in modern integrated circuits, aluminum-based metal lines are increasingly being replaced by copper-based metal lines, wherein the copper-based metal lines are typically embedded in a dielectric material having a reduced relative permittivity in the range of, for example, less than approximately 3.1, which are also referred to herein as low-k dielectric materials. The metal lines, which provide the electrical connection between the circuit elements in accordance with the specified circuit design, typically are also reduced in dimension when the corresponding feature sizes of the circuit elements are scaled down. The metal lines are typically arranged in several levels, also referred to as metallization layers, which are stacked upon each other, wherein the electrical connection between individual metallization layers is obtained by so-called vias. Due to the reduced dimensions of the metal lines and vias, moderately high current densities are typically encountered during the operation of modern integrated circuits, which require precise control of the metal lines and vias in order to not unduly deteriorate device reliability caused by line failure, increased leakage currents, and the like.
With reference to FIGS. 1a-1d, a conventional process sequence will now be described in more detail, in which the problems are explained occurring on the transition from a well established manufacturing sequence with a 248-nm-based process to a 193-nm-based process for metal lines in the first metallization layer.
In FIG. 1a, a semiconductor device 100 comprises a substrate 101, on which is formed a circuit element 102. A first dielectric layer 103 is formed above the substrate 101 and encloses the circuit element 102. In the first dielectric layer 103, a contact element 104 is formed of an electrically conductive material comprising, for instance, tungsten, tungsten silicide, and the like, wherein the contact element 104 extends through the first dielectric layer 103 to provide electrical contact to the circuit element 102 or a portion thereof. Hence, the first dielectric layer 103, which is comprised of silicon dioxide and/or silicon nitride, electrically insulates the contact element 104 and the circuit element 102 from any neighboring contact elements and circuit elements (not shown). Located above the first dielectric layer 103 is a dielectric etch stop layer 105, which is comprised of a dielectric material having a low permittivity as is required to reduce the parasitic capacitance of neighboring electrical connections still to be formed. For instance, frequently the etch stop layer 105, which is commonly referred to as a BLOK (buried low-k) layer, is comprised of silicon, carbon and nitrogen in the form of an SiCN layer. A second dielectric layer 106 comprised of a low-k dielectric material, such as a silicon, carbon, oxygen and hydrogen containing layer with the chemical formula SiCOH, is formed above the etch stop layer 105, followed by a capping layer 107. The capping layer 107 may be comprised of two sub-layers 108 and 109, wherein the sub-layer 108 may be formed of silicon dioxide for strengthening a surface of the mechanically less stable low-k dielectric layer 106. The second sub-layer 109 may substantially serve as an ARC layer during the lithography process to be performed later for forming a trench in the capping layer 107, the low-k dielectric layer 106 and the etch stop layer 105. Hence, the composition and the thickness of the ARC layer 109 is selected in conformity with the exposure wavelength used in the subsequent lithography to minimize back reflection and standing wave effects. As previously noted, with the advance to a new technology node, for instance the transition from the 130 nm to the 90 nm technology, the dimensions of metal lines to be formed in the stack of layers 105, 106 and 107, also have to be significantly reduced, for instance by about 25%, wherein also an exposure wavelength of 193 nm may be applied instead of 248 nm. For this reason, the corresponding dimensions, i.e., the thicknesses of the layers 105, 106, 107 are adapted to the new design requirements and the newly used exposure wavelength starting from the well approved layer stack arrangement employed in the 130 nm technology using the 248 nm exposure wavelength. Typical dimensions obtained from transferring the 130 nm technology to a 90 nm technology may be approximately 50 nm for a thickness 105a of the etch stop layer 105, approximately 150 nm for a thickness 106a of the low-k dielectric layer 106, approximately 80 nm for a thickness 108a of the layer 108 when comprised of silicon dioxide and approximately 60 nm for a thickness 109a for the ARC layer 109 when comprised of silicon oxynitride.
A typical conventional process for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. First, the circuit element 102 is formed in and on the substrate 101 by known process techniques involving highly advanced photo-lithography using a 193 nm exposure wavelength, sophisticated etch, deposition, implantation and polishing sequences, which will not be referred to in detail herein. Thereafter, the first dielectric layer 103 may be formed by well-established plasma enhanced chemical vapor deposition (PECVD) techniques, possibly in combination with chemical mechanical polishing processes. Then, the contact element 104 is formed by highly advanced photolithography, etch and deposition techniques to first form a contact opening, which is then filled by a conductive material such as tungsten, tungsten silicide, and the like. Excess material of the contact element 104 may be removed by, for instance, chemical mechanical polishing as is well known in the art. Thereafter, the first etch stop layer 105 is deposited with the specified thickness 105a in conformity with well-established process recipes. Next, the low-k dielectric layer 106 is formed, in the present case, by depositing SiCOH from appropriate precursors by PECVD, with a thickness that is in conformity with device requirements. Thereafter, the silicon dioxide layer 108 may be deposited followed by the deposition of the ARC layer 109, which may both be deposited by well established PECVD techniques.
FIG. 1b schematically shows the semiconductor device 100 having formed thereon a resist mask 110 with an opening 111 substantially having the dimensions of a trench 112 that is to be formed in the capping layer 107, the low-k dielectric layer 106 and in the etch stop layer 105 in a subsequent etch process. The resist mask 110 is comprised of a resist material that is highly sensitive to an exposure wavelength of 193 nm and which also provides a moderate high etch selectivity during subsequent etch processes. Moreover, a thickness 110a of the resist mask 110 is selected to achieve an acceptable compromise between a high layer thickness for an enhanced masking effect in the subsequent etch process, as significant material removal is also generated in the resist mask 110 during the progress of the etch process, and the optical and development behavior of the resist during the lithography process. Hence, the thickness 110a may be selected to be approximately 320 nm. The resist mask 110 is formed in accordance with known lithography techniques using apparatus with 193 nm exposure wavelength, wherein the characteristics of the resist in combination with the ARC layer 109 and the silicon dioxide layer 108 enable the formation of the opening 111 having a lateral dimension significantly less than 193 nm. As it may readily be appreciated, any pre- and post-exposure treatments and pre- and post-development treatments may be performed in accordance with well-established recipes. Thereafter, the resist mask 110 is used to form the trench 112 during a highly anisotropic etch process.
FIG. 1c schematically shows the device 100 in an advanced stage of an anisotropic etch process, indicated as 120, wherein the trench 112 is already etched down to the etch stop layer 105. The conventional anisotropic etch process 120 includes three steps, wherein a first step is performed with a specified etch chemistry containing CHF3 and oxygen to form the trench 112 in the capping layer 107. Thereafter, the etch chemistry is changed for a second or main etch step to achieve a desired removal rate and a substantially anisotropic material removal during forming the trench 112 through the low-k dielectric layer 106. The etch chemistry used during this second etch step may be based on C4F8, argon and nitrogen and a moderately high plasma power. As is evident from FIG. 1c, during the first and second etch steps, material of the resist mask 110 is also removed, wherein particularly edge regions 113 suffer from an increased material removal so that the edges of the capping layer 107 are preferably exposed to the etch attack. The main etch through the low-k dielectric layer 106 stops on and within the etch stop layer 105, wherein the material removal of the etch stop layer 105 may be monitored by a characteristic change of an endpoint detection signal that may be obtained by spectroscopic measurements of the gaseous by-products liberated during the etch process. At this time, the etch chemistry may be changed to efficiently open the etch stop layer 105, thereby completing the trench 112. Again, during this final etch step, which is typically performed with a reduced anisotropic behavior, the edge regions 113 are preferably attacked by the etchant. As previously noted, since the thickness 110a of the resist mask 110 may not be increased arbitrarily to substantially reduce the erosion of the edge regions 113, especially during the final etch step for opening the etch stop layer 105, owing to lithographical constraints, a high roughness at the trench edge is obtained, which may finally lead to increased leakage current and reduced line reliability, after coating the trench 112 with a barrier material and filling it with a metal, such as copper.
FIG. 1d schematically shows a top view of a plurality of trenches 112 having the edge regions 113, which exhibit a pronounced roughness, thereby causing the above-noted disadvantages.
In view of the line deterioration caused by the pronounced roughness of the edge regions of metal lines, there exists a need for an improved technique that enables the formation of trenches with reduced edge roughness even for manufacturing technology using an exposure wavelength of less than 248 nm.